1. Field of the Invention
The present invention. relates to a semiconductor device and a method for manufacturing the same. Particularly, the present invention relates to a semiconductor device having the multi-layer wiring structure, wherein a plurality of wiring layers are deposited on top of another, through an interlayer insulating film, and a method for manufacturing the same.
2. Description of the Related Art
Every year, along with the miniaturization of integrated circuits included in semiconductor devices, the integration degree of such integrated circuits has been increased. To realize the high integration of the integrated circuits, the multi-layer wiring structure including a plurality of wiring layers formed on top of another is employed. The plurality of wiring layers are deposited on top of another through an interlayer insulating film, and connected with each other through a via hole (or a contact hole) formed in the interlayer insulating film.
Such a semiconductor device having the multi-layer wiring structure is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H4-372157. As shown in FIG. 3, in the semiconductor device disclosed in the above publication, a lower interlayer insulating film 32 having a via hole 32A is formed on a substrate 31. A metal film 33 for the lower wiring layer is formed over and throughout the surface of the lower interlayer insulating film 32 and the internal wall and bottom of the via hole 32A. An upper interlayer insulating film 37 having a via hole 37A is formed on the metal film 33. A metal film 38 for the upper wiring is formed over and throughout the surface of the upper interlayer insulating film 37 and the internal wall and bottom of the via hole 37A. The metal film 38 is electrically connected to the metal film 33 through the via hole 37A.
The formation position of the via hole 32A and the formation position of the via hole 37A do not vertically coincide with each other. Hence, it is hard to miniaturize the semiconductor device having the above structure shown in FIG. 3.
If the semiconductor device is made in a miniaturized form, and the integration degree is raised, the aspect ratio of the via hole is set high. In the case where a wiring layer is formed on an interlayer insulating film having a via hole with a high aspect ratio, using a sputtering technique, etc., a void may possibly be created inside the via hole by a shadowing effect.
If the wiring layer is etched while leaving the void inside the via hole, the void is expanded so that a layer (e.g., a substrate) below the interlayer insulating film may unintentionally be etched as well. As a result of this, the semiconductor device can not desirably be operated.
According to a technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H5-304216, the via hole is filled with silicon oxide, thereby the semiconductor device is prevented from any effect of the void.
Particularly, as illustrated in FIG. 4, an interlayer insulating film 42 is formed on a lower wiring layer 41. A metal film 43 is formed, using a sputtering technique, on the interlayer insulating film 42 and inside the via hole which is formed in a predetermined position of the interlayer insulating film 42. The via hole is filled with silicon oxide 45, after the formation of the metal film 43. The upper wiring layer 44 is formed on the metal layer 43 and the silicon oxide 45, using a sputtering technique. In this structure, the upper wiring layer 44 is electrically connected to the lower wiring layer 41 through the metal film 43.
As shown in FIG. 4, in the structure the via hole is mostly filled with the silicon oxide 45, a problem is that the resistance between the lower wiring layer 41 and the metal film 43 through the via hole is high.
In the case where another via hole is formed just above the via hole of the interlayer insulating film 42, the upper wiring layer 44 may be over-etched. Hence, the semiconductor device can not desirably be operated.
The entire contents of Unexamined Japanese Patent Application KOKAI Publications Nos.H4-372157: and H5-304216 are herein incorporated in this specification.
It is accordingly an object of the present invention to provide a semiconductor device having high operational reliability and a manufacturing method therefor.
Another object thereof is to provide a semiconductor device which gets no effect of a void created inside a via hole.
Still another object thereof is to provide a method for manufacturing a semiconductor device which is prevented from getting any effect of a void created inside a via hole.
In order to achieve the above objects, according to the first aspect of the present invention, there is provided a method for manufacturing a semiconductor device having at least two via holes which vertically meet each other, the method comprising:
forming a first via hole in a first interlayer insulating film;
forming a barrier metal on a surface of the first interlayer insulating film and a side wall and bottom of the first via hole;
filling the first via hole with a first conductive material, by depositing the first conductive material on the barrier metal;
filling, with a filling material, a void, which is formed inside the first via hole by filling the via hole with the first conductive material;
etching a barrier metal which is formed on the surface of the first interlayer insulating film;
forming a second interlayer insulating film on the first interlayer insulating film;
forming a second via hole and removing the filling material from the void, by etching an area above the first via hole of the second interlayer insulating film; and
filling the second via hole and the void with a second conductive material.
According to this invention, a semiconductor device which does not get any effect from the void which is created inside the via hole can be manufactured. As a result of this, it is possible to provide a semiconductor device having high operational reliability.
The filling the void with the filling material may include using the filling material having fluidity.
The filling the void with the filling material may include filling the void with the filling material using an SOG (Spin On Glass) technique.
The filling the void with the filling material may include using the filling material including a substance which is not substantially etched by a substance for etching the barrier metal.
The filling the void with the filling material may include filling the void with the filling material and forming a reflection preventing film, on the barrier metal, for etching a predetermined area of the barrier metal, by depositing the filling material on the barrier metal and the conductive material which is filled in the first via hole.
The filling the void with the filling material may include depositing SiON inside the void, as the filling material, using a plasma CVD (Chemical Vapor Deposition) technique.
The depositing the SiON may include depositing the SiON in such a manner that a thickness of the reflection preventing film is in a range from 30 to 100 nm.
The forming the barrier meal may include
forming a Ti film over and throughout the surface of the first interlayer insulating film and the side wall and bottom of the first via hole, and
forming a TiN film on the Ti film;
the filling the void with the filling material includes using the filling material including a silicon oxide; and
the etching the barrier metal may include etching the barrier metal with a chloric gas.
In order to achieve the above objects, according to the second aspect of the present invention, there is provided a semiconductor device having at least two via holes which vertically meet each other, the device comprising:
a first interlayer insulating film which includes a first via hole;
a second interlayer insulating film which is formed on the first interlayer insulating film and includes a second via hole in an area above the first via hole;
a first conductive material which is deposited inside the first via hole; and
a second conductive material which is deposited inside a void, created when depositing the first conductive material, and the second via hole.
The first via hole may have a diameter in a range from 0.28 to 0.32 xcexcm.